Items to discuss this Friday

1. With Mr. W
1. What is the "outer cache" in Enable/Disable L2CC commands? Why do you need a mutex in a page in SHM? Is it only with HYP, or else How does it work with multi Guests (Guest Client IDs)?
2. Should SHM validation happen in  tee_mmu_check_access_rights() in optee_os/core/arch/arm/mm/tee_mmu.c?
3. Is the entire DDR mapped in SEL1 page table (secure TTBR1)?
2. With Mr. D and Mr. Z:
1. fault model to register events from S1 PTW faults in S2
2. Driver model in EL2
3. Ownership transfer of device "objects"